1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which defective memory cells can be replaced with redundant cells.
2. Description of Related Art
Semiconductor memories typified by a DRAM (Dynamic Random Access Memory) include a large number of memory cells, some of which inevitably become defective due to manufacturing conditions and other factors. In order to ship such semiconductor memories as conforming products, the redundancy repair technique of replacing defective memory cells with redundant cells is needed.
According to the redundancy repair technique, a semiconductor memory in a wafer state is initially subjected to an operation test to detect the addresses of defective memory cells (defect addresses). The detected addresses are programmed into optical fuses in the semiconductor memory. Optical fuses are fuses that can be blown by irradiation of a laser beam or the like. Since blown optical fuses cannot be restored to a conducting state again, it is possible to store information in a nonvolatile and irreversible manner. When access is requested to the addresses programmed in the optical fuses, redundant cells (alternative cells) are accessed instead of the defective memory cells, whereby the addresses are repaired.
Memory cell defects occur mainly in the wafer stage (manufacturing steps for forming a plurality of circuits on a wafer; so-called front-end processes). Most defects are therefore repaired by replacement using optical fuses. However, new defects can occur after the replacement using optical fuses, in back-end processes including assembly. For example, new defects may occur due to a thermal load during packaging. It is not possible to repair such defects by using the optical fuses.
As a solution to the problem, Japanese Patent Application Laid-Open No. 2002-25289 (Patent Document 1) proposes a semiconductor device that can implement both the replacement using optical fuses and replacement using electrical fuses. The semiconductor device described in Patent Document 1, however, has had the problem that the need to provide both optical fuses and electrical fuses in a single chip increases the die size.
Japanese Patent Application Laid-Open No. 2007-328914 (Patent Document 2) proposes a method of storing post-packaging defective addresses of a volatile memory (first semiconductor device) into a nonvolatile memory (second semiconductor device) which is mounted on the same module substrate, and loading the defective addresses from the second semiconductor device to the first semiconductor device at startup. According to such a method, the volatile memory to be repaired, such as a DRAM, need not include electrical fuses. It is therefore possible to suppress the increase in die size.
According to the method described in Patent Document 2, however, defective addresses are loaded through external terminals of the first semiconductor device. The inventors have recognized that it interfered with an initialization operation between a memory controller and the memory module impossible during the loading period. An event therefore arises since it takes time to start up the memory module.